1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device that writes information stored based on the resistance state of a variable resistive element in memory cells by applying a voltage pulse.
2. Description of the Related Art
In recent years new types of nonvolatile semiconductor memory devices for replacing flash memories have been widely researched. In particular, RRAM's using the change in the resistance when a voltage is applied to a variable resistive film, such as of a transition metal oxide, have an advantage in that there are less limitations in terms of how much they can be miniaturized in comparison with flash memories, and make it possible to write data at a high speed, and thus, research and development are being actively carried out.
As shown in Japanese Unexamined Patent Publication 2002-151661, the conventional structure of memory cell arrays using RRAM's is of a 1T1R type, which can prevent a leak current and a roundabout current from flowing through unselected memory cells when information stored in the variable resistive element in the selected memory cell is written and read out by connecting a transistor for selecting a cell to the variable resistive element of the memory cells in series.
FIG. 12 shows the configuration of the cell array of conventional RRAM's. In the memory cell array 200, variable resistive elements R11 to R1n, R21 to R2n and so on, and transistors for selecting a cell Q11 to Q1n, Q21 to Q2n and so on are aligned in a matrix shape in the column direction (lateral direction in the figure) and the row direction (longitudinal direction in the figure). In each memory cell, a first end of the variable resistive element and a first end of the transistor are connected, a second end of the variable resistive element of memory cells aligned in the same column is connected to a bit line BL1, BL2 and so on, which run in the column direction, a second end of the transistor of memory cells aligned in the same row is connected to the common line CML, which is shared by all the memory cells, and word lines WL1 to WLn, which run in the row direction, are respectively connected to the gate terminals of the transistors in the memory cells aligned in the same row.
External power supply lines V1 and V2 for supplying a writing voltage are connected so that the voltage in the power supply line V1 and the voltage in the power supply line V2 are applied to the bit lines BL1, BL2 and so on, and the common line CML, respectively, via the transistors in the writing voltage applying circuit 201. In addition, bit lines BL1, BL2 and so on, and the common line CML are connected via the transistors in the initialization circuit 202, and the voltage is applied to the bit lines from the common line, so that it is possible to initialize the voltage of bit lines that become of a previous writing operation voltage state due to the effects of the parasitic capacitance between wires, for example between bit lines and variable resistive elements connected to the bit lines.
FIG. 13 shows the timing chart upon writing the variable resistive element R11 shown in FIG. 12. Hereinafter the operation for lowering the resistance of the variable resistive element is referred to as setting (programming), through which the current flowing through the memory cell increases, and the operation for raising the resistance of the variable resistive element is referred to as resetting (erasing), through which the current flowing through the memory cell is made small. The definition of setting and resetting may, of course, be the opposite. In addition, combined operation of setting and resetting is referred to as writing.
At time t1, the voltage applied to the word line WL1 is raised to a voltage VWLS (typically 4 V) at the time of setting and to a voltage VWLR (typically 6 V) at the time of resetting, and after that, at time t2, φ1, φ2 and φ5 are raised, and the initialization operation is carried out. That is to say, the voltage of the power supply line V1 is applied to the selected bit line BL1 and the voltage of the power supply line V2 is applied to the common line CML via the transistors in the writing voltage applying circuit 201, and furthermore, the same voltage as for the common line CML is applied to the unselected bit lines BL2 and so on via the transistors in the initialization circuit 202, so that the voltage of the unselected bit lines is initialized. At this time, the voltage of the power supply lines V1 and V2 is the same initialization voltage VPRE (typically 1.5 V), and as a result, the common line CML and all of the bit lines BL1, BL2 and so on are pre-charged to the same voltage VPRE.
After that, at time t5 to t6, a writing voltage pulse is applied to the power supply lines V1 and V2. That is to say, at the time of setting, the voltage in the power supply line V1 is converted to a voltage VSET (typically 3V) and the voltage in the power supply line V2 is converted to GND, so that a current flows from the selected bit line BL1 to the common line CML via R11 and Q11. Meanwhile, at the time of resetting, the voltage in the power supply line V1 is converted to GND and the voltage of the power supply line V2 is converted to a voltage VRST (typically 3 V), so that a current flows from the common line CML to the selected bit line BL1 via Q11 and R11.
Although in the array structure shown in FIG. 12, the leak current and the roundabout current can be prevented from flowing through unselected memory cells, a voltage is applied to adjacent unselected memory cells when writing is repeated in the selected memory cell, and thus, a so-called writing disturbance, where information in adjacent memory cells is written, cannot be prevented. Writing disturbances can be divided into three categories in accordance with its cause. In the following, the three types of writing disturbances are described in reference with FIG. 12, which shows the array structure, and FIG. 13, which is a timing chart for the writing.
First, the first type of writing disturbance is “selected bit line disturbance”, which is caused in unselected variable resistive elements R12 to R1n which are connected to the selected bit line BL1 when the writing voltage pulse is applied to the power supply line V1 at time t5, so that the voltage in the selected bit line BL1 changes. For example, in the unselected variable resistive element R12, there is a parasitic capacitance, although small, in the connection point node #A between the variable resistive element R12 and the cell transistor Q12. Since the transistor Q12 connected to the unselected word line WL2 is turned off, the node #A is connected only to the selected bit line BL1 via the variable resistive element R12. Accordingly, when the voltage of the selected bit line BL1 fluctuates, this fluctuation is conveyed to the node #A with a delay of time constant RC (typically 10 ns), which is determined by the resistance value R of the variable resistive element R12 (typically 1 MΩ when the RRAM is in a high resistance state) and the parasitic capacitance C at the node #A (typically 10 fF). Therefore, there is a difference in potential which corresponds to the delay in the voltage fluctuation between the two ends of the variable resistive element R12.
Next, the second type of writing disturbance is “unselected bit line disturbance”, which is caused in variable resistive elements R22 to R2n and so on connected to the unselected bit lines BL2 and so on. This is because φ5 remains high when the writing voltage pulse is applied to the power supply line V2 at time t5, so that the voltage in the common line CML changes, and therefore, the voltage in the unselected bit lines BL2 and so on changes to the same voltage as in the common line CML. In the variable resistive element R22, there is a parasitic capacitance C, although small, at the connection point node #B between the variable resistive element R22 and the transistor Q22. Since the transistor Q22 connected to an unselected word line WL2 is turned off, the node #B is connected only to the unselected bit line BL2 via the variable resistive element R22. Accordingly, when the voltage of the unselected bit line BL2 fluctuates, this fluctuation is conveyed to the node #B with a delay in the time constant RC (typically 10 ns), which is determined by the resistance value R of the variable resistive element R22 (typically 1 MΩ when the RRAM is in a high resistance state) and the parasitic capacitance C at the node B (typically 10 fF). Therefore, there is a difference in potential which corresponds to the delay in the voltage fluctuation between the two ends of the variable resistive element R22.
FIG. 14 shows bit line noise 203 caused by the selected bit line disturbance or unselected bit line disturbance, which is the absolute value of the voltage fluctuation that is applied across the two ends of the variable resistive element R12 or R22. These are the results of a simulation for a case where a writing voltage pulse of +2V is applied to the selected bit line BL1 or the unselected bit line BL2 for 50 ns with an initialization time of 2 ns, and it is clear from this that a pulse with a peak voltage of 1.8 V having a width of 10 ns at half height is also applied to unselected memory cells. This is sufficiently large disturbance in comparison with the width of the writing pulse applied to selected cells, which is approximately 50 ns.
In order to prevent “unselected bit line disturbance”, which is the second type of writing disturbance, it is desirable to make the voltage fluctuation in non-selected bit lines via the common line as soft as possible. However, the delay in the conveyance of the signal between wires causes a difference in the change in voltage between unselected bit lines BL2 and so on and the common line CML, and as a result, the difference in potential is applied to variable resistive elements R21 and so on aligned in the row direction along the selected word line WL1. This is because the cell transistors Q21 and so on connected to the selected word line WL1 are turned on in these variable resistive elements. For example, the voltage fluctuation in the unselected bit line BL2 via the common line is conveyed to the node #C with a delay of time constant RC (typically 1 μs), which is determined by the resistance value R in the variable resistive element R21 (typically 1 MΩ) when the RRAM is in a high resistance state) and the parasitic capacitance C between wires (typically 1 pF). As a result, a difference in potential that corresponds to the delay in the voltage fluctuation between the unselected bit line BL2 and the common line CML is applied across the two ends of the variable resistive element R21.
This is the third type of writing disturbance, which is hereinafter referred to as “common line disturbance”. Common line noise 204 in FIG. 14 shows the absolute value of the voltage fluctuation that is applied across the two ends of the variable resistive element R21 in the case where the voltage fluctuation of the unselected bit lines is very slow. These are the results of a simulation for a case where a writing voltage pulse of +2 V having an time for initialization of 2 ns is applied to the common line for 50 ns, where the writing voltage ends up being applied to unselected memory cells for a long period of time. As is clear from the above, “the common line disturbance” and “the unselected bit line disturbance” are related in that when one is suppressed the other grows, and therefore, it is very difficult to provide a design that is appropriate to suppress both.
As a measure for suppressing the above describe disturbances, Japanese Unexamined Patent Publication 2004-185755 discloses a method according to which the transistors of individual memory cells are connected to bit lines and the variable resistive elements of individual memory cells are connected to the common line (source line), so that a writing voltage pulse can be applied from the bit line side. In this method, although the disturbance can be suppressed in the case where a writing voltage pulse is applied from the bit line side, the disturbance cannot be suppressed in the case where a writing voltage pulse is applied from the common line side. Particularly in the case where variable resistive elements having bipolar properties are used for storing information, the setting operation and the resetting operation are carried out by applying a voltage pulse of a different polarity, and therefore, it becomes necessary to apply a writing voltage pulse from the common line side, and in this case, the writing disturbance cannot be suppressed completely.
In order to completely suppress the disturbances, two cell transistors for selecting a memory cell are provided and connected to the two ends of the variable resistive element in the memory cell, as shown in FIG. 4 in Japanese Unexamined Patent Publication 2004-185755. However, three elements are required per cell, and the area for the cell array becomes large.
Incidentally, semiconductor memory devices using variable resistive elements for storing information are expected to be used as nonvolatile memories for storing digital camera images and nonvolatile memories for cellular phones and other electronics. When used as a nonvolatile memory for a digital camera, however, it is necessary to keep the chip area small in order to lower the cost per bit. Furthermore, even a one-pixel error lowers the quality of the image stored in the nonvolatile memory, and therefore, the reliability of the data must be kept high when stored. Moreover, the reliability of the data must be kept high when stored for a long period of time. In addition, when used as a nonvolatile memory in other electronics, for example in a cellular phone, a communication protocol is recorded together with image data, and therefore, the data has to be highly reliable.
That is to say, although it is desired for the above-described semiconductor memory device to be put into practice as a nonvolatile memory which is highly reliable when written, the writing disturbance cannot be suppressed without increasing the cell array area as long as the memory cell array has a conventional structure, and thus, a highly reliable nonvolatile memory cannot be implemented while preventing the cell array area from being large.